Crystal Oscillator Terms

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Crystal Oscillator Terms

**Nominal frequency:**

The center or nominal frequency of a crystal oscillator.

**Frequency stability:**

Deviation from the nominal output frequency including the frequency deviation due to manufacturing process, temperature, power source variation and load variation. The most common stabilities are±25, ±50 and ±00ppm.

**Operating temperature range**

Temperature range within which output frequency stability and other electrical, Environmental characteristics meet the specifications. Military: -55℃ to+125℃; Industrial:-40℃ to+85℃;commercial: 0℃ to+70℃.

**Frequency aging:**

The relative frequency change over a certain period of time. The rate of change ofFrequency is normally exponential in character. Typically, aging is ±5 ppm maximum over 1 year.

**Storage temperature:**

The temperature range within which the unit is safely stored without damaging orChanging the performance of the unit.

**Oscillator output:**

The output of a hybrid crystal oscillator is a highly stable reference signal and it can formsquare wave of HCMOS or TTL level, depending on the technology of the active devices used in the circuit.Output logic: The vast majority of systems require a crystal oscillator output that is TTL compatible, CMOSCompatible, ECL compatible or some combinations of logic families such as TTL/HCMOS compatible.

**TTL/HCMOS compatible:**

The oscillator is designed with ACMOS logic with driving capability of TTL andHCMOS loads while maintaining minimum logic HIGH of the HCMOS.

**Logic levels:**

Logic levels may be positive or negative. Positive logic is assumed when logic 1 level is morePositive than logic 0 level, while negative logic is assumed when the logic 1 level is more negative than logic 0 Level.

**Output HIGH voltage (VOH):**

The minimum voltage at output logic 1 state of the oscillator under properLoading.

**Output LOW voltage (VOL):**

The maximum voltage at output logic 1 state of the oscillator under properLoading.

**Fan out (Loads):**

The measure of the driving capability of an oscillator, expressed as the number of inputs thatcan be driven by a single output. It can be represented by an equivalent load capacitance specified at pF inCMOS logic or the number of gates in TTl load circuit consisting of diode, load resistors, and a capacitor. If This value exceeds the maximum rated load of the oscillator, signal degradation can occur.

**Startup time:**

The startup time is specified as the that an oscillator take to reach its specified RF output amplitude. The startup time is determined by the closed loop time constant and the loading condition of its circuit.

**Rise & Fall time (Tr & Tf):**

The rise time Tr of an oscillator is defined as the transition time of the output waveform from low stage (logic 0 ) to high stage (logic 1 ). The fall time Tf of an oscillator is defined as the transition time of the output waveform from high stage (logic 1 ) to low stage (logic 0 ). The transition times measured at the specified level such as between 90% and 10% of the falling edge of the switching waveform for HCMOS device. Increasing the load will increase the rise and fall times of the device.

**Symmetry or Duty cycle:**

The measure of output waveform uniformity of the shape of the waveform, which is made up of logic 1 and logic 0 cycle times. It is defined as the ratio of the time periods of the logic 1 level (TH) to the time periods of one complete cycle (T), measured at 1.4 volts for TTL logic and 50% of the peak-to-peak voltage for CMOS. Sym=TH/T X 100%.

**Tri-state enable:**

By applying a command input signal to the oscillators, the output of the clock oscillators is turned off or disabled. When this feature is activated, the oscillators assume a high impedance state. This feature allows the oscillator to be isolated from the circuit upon application of a command signal.

**Input current ad supply voltage:**

Input current is the amount of current deain by an oscillator in its operating condition. Different logic oscillators require different input current. Supply voltage is the voltage necessary to operate the oscillator. It is typically 5 V or 3.3 V.

**Phase Noise:**

Phase noise is a small fraction of undesirable frequency near the output frequency, and is usually Expressed as the single side band (SSB) power density density in a 1 Hz bandwidth at a specified oddest frequency from The carrier. It is measure in dBc/Hz.

**Jitter:**

Measure of the modulation in phase or frequency of the oscillator output.

**Standby function**:

A function built in the IC that temporary turns off the oscillator to save power. Logic 0 will enable stand by mode. The disable current at stand by mode varies from few micro ampered to tens of micro amperes (0.005 mA typical). Because oscillation is halted, there is a maximum of 10ms (same amount as the start-up time) before output stabilizes.

**Harmonic distortion**:

The non-linear distortion due to un-wanted harmonic spectrum component related with Target signal frequency. Each harmonic componic component is the ratio of electric power against desired signal outputelectric power and expressed in terms of dBc. The non-linear distortion due to un-wanted harmonic spectrum component related with Target signal frequency. Each harmonic componic component is the ratio of electric power against desired signal outputelectric power and expressed in terms of dBc.

**Drive Level (DLD)**

The amplitude of mechanical vibration of the quartz resonator increases proportionally to the amplitude of the applied current. The power dissipated in the resonance resistance is given by Pc=12q R1 . High drive levels lead to the destruction of the resonator or the vaporization of the evaporated electrodes, The upper limit for drive level is approximately 10mW. As the reactive power oscillating between L1 and C1 is represent red by Qc =Q X Pc, for Pc=1 Mw and with a Q of 100.000, Qc is equal to 100Watts, The oscillation amplitude can be excreted with relatively low level of drive Pc, thus resulting in the crystal frequency moving upwards.

This frequency dependence on drive level is more pronounced with increasing overtone order. The crystal unit is an electronic device that is capable of composing a frequency generator circuit with an extremely high stability .It has achieved high degree of compactness and high performance . Fig 5. Shows typical effects but exact prediction of the effect is not possible as it is influenced by all the elements of crystal design and operation. Mechanical blank parameters, electrode size, mounting arrangements and so on. Is it can be seen that the drive level must be specified carefully, if there is to be good correlation between the frequency of the crystal at the end of its production and in the end use equipment.

Today with semiconductor oscillator circuits a drive level of approximately 0.1Mw appears normal, Where this Parameter is most specified, our production will use 0.1mW. A well performing crystal should start to oscillate easily and its frequency should be virtually independent of the variation of drive level from a starting level of About 1 n W. In toadies semiconductor circuits with very low power consumption the crystal has to work well also at vet low drive levels.In Fig. 6 we show the effect of crystals with and without the problem of frequency dependence on drive level.Crystal that have badly adhering electrodes or on which the surface of the resonator is not fine enough exhibit the curved effect. At low drive levels they have higher resistance. This effect is called the drive level dependence (DLD). Usually production tests of DLD are performed between 1 and 10 microwatts and then at 1 Mw and again at a low load. The relative change in resistance is then used as the test criterion. Needless to say, making more easurements at intermediate level increases crystal production costs considerably.

Using suitable test oscillators permits fast testing of the DLD limit value, but only in the form of a Go/No-go test. IEC Draft 248 covers measurement of the drive level dependence of the resonance impedance in accordance with (DIN) IEC444-6. Oscillation bull-up problems can very largely be eliminated by optimizing the oscillator circuit by providing a sufficient feedback serve and a "hard" switch-on pulse.

**Equivalent Circuit**

When a crystal unit is actuated as an inductive reactance in an oscillation circuit, the relationship between crystal unit and oscillation circuit is shown in Fig.8.To improve the starting conditions of the oscillation circuit, it is preferable to increase the value of negative resistance -R which parameter of the oscillation circuit .

The starting conditions will become worse if a circuit without much allowance in negative resistance (less negative resistance )is combined with a crystal unit having a larger resonance resistance. The oscillation circuit should be designed to A goal such that the value of negative resistance is 5 to 10 times the resonance resistance.

It is also necessary that the center value of load capacitance (to determine the absolute value of oscillation frequency )and the variable range (fine adjustment range of oscillation frequency) are maintained at the optimum values in the Oscillation circuit.

**Freq. Temp. Characteristics**

The frequency-temperature characteristics of an AT-Cut crystal unit most generally used at present are expressed by cubic curves. (See Fig.3 & Fig.4)A crystal plate is cut at an angle at which a required frequency tolerance is obtained in the given operating temperature range.

**Load Capacitance (CL)**

The load capacitance CL is a factor for determining the "conditions"of a crystal unit when used in the oscillation circuit .In an ordingay oscillation circuit the crystal unit is used in a range where it functions as an inductive reactance in such usage ,the oscillation circuit operates as a capacitive reactance .

In other words ,when the oscillation circuit is seen from both terminals of the crystal unit, this oscillation circuit can be expressed as a series circuit of a negative resistance -R and a capacitance CL . At that time this capacitance is called the load capacitance .The relationship between load capacitance and oscillation frequency is not linear.

When the load capacitance is small, the amount of frequency variation is large ,and when the load capacitance is increased, frequency variation lowers .If the load capacitance is lessened in the oscillation circuit to secure a large allowance for the oscillation frequency ,the frequency stability will be greatly influenced even by a small change in the circuit. The load capacitance can be chosen from standard values specified in the catalog. but 10-30pF is better.

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